Ultra-Low Latency Ethernet MAC/PCS FPGA IP Cores
Deterministic FPGA Ethernet IP Cores connectivity supporting 1G, 10G, 25G, 40G and 100G line rates with best-in-class latency and throughput performance.
As data rates grow and latency budgets shrink, traditional software networking stacks struggle to maintain deterministic performance. Packet processing delays, jitter, and CPU overhead quickly become system-level bottlenecks.
Ethernet MAC/PCS IP cores for FPGA developers
Benefits
- Best in-class latency and throughput performance
- Highly optimized implementation supporting multiple SERDES data bus width options
- Ultra-low gate count and resources utilization
- Excellent timing margin including a rich set of standard and advanced features
- Based on a unified Verilog code solution that scales from 1-Gbps to 100-Gbps data rate
- Unified Verilog source code and UVM environment
- Compliant with the IEEE 802.3 High Speed Ethernet Standard
Key Features
Advanced features for 1-Gbps to 100-Gbps data rates
- Multi-Speed Ethernet Support
- Deterministic Throughput & Packet Processing
- PCS & Transceiver Integration
- Error Correction & Reliability
- Network & Traffic Management
- Monitoring & Statistics
FPGA DEVICE UTILIZATION AND PERFORMANCE:
1G MAC & PCS
Wire to Wire Round-Trip Latency (1)
136ns
Device Family (2)
UltraScale +
Rate [Gbps]
1-Gbps
Resources Utilization (3)
LUTs
2.28k
FFs
4.14k
BRAM
0
Core clock [MHz]
250
Latency Measurements
TxSoP to RxSoP
Wire to Wire Round-Trip Latency (1)
64ns
Device Family (2)
UltraScale +
Rate [Gbps]
1-Gbps
Resources Utilization (3)
LUTs
2.28k
FFs
4.14k
BRAM
0
Core clock [MHz]
250
Latency Measurements
TxSoP to RxSoF
(1) Latency: GTY Transceiver + PCS + MAC (Tx+Rx)
(2) Other FPGA platforms supported
(3) Resources utilization includes statistics counters
(2) Other FPGA platforms supported
(3) Resources utilization includes statistics counters
10G MAC & PCS
Wire to Wire Round-Trip Latency (1)
17.1ns
Device Family
UltraScale +
Rate [Gbps]
10-Gbps
SERDES Width
16b
AXI-4 Stream Width
16b
Resources Utilization
LUTs
1.4k
FFs
1.1k
BRAM
0
Core clock [MHz]
644.531
Wire to Wire Round-Trip Latency (2)
34.1ns
Device Family
UltraScale +
Rate [Gbps]
10-Gbps
SERDES Width
16b
AXI-4 Stream Width
32b
Resources Utilization
LUTs
1.5k
FFs
1.1k
BRAM
0
Core clock [MHz]
644.531
(1) Latency: GTY + MAC/PCS (Measured from TxSoP to RxSoF using serial loopback)
(2) Latency: GTY + MAC/PCS + CDC(Measured from TxSoP to RxSoP using serial loopback)
(2) Latency: GTY + MAC/PCS + CDC(Measured from TxSoP to RxSoP using serial loopback)
25G MAC/PCS
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
114ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
4.98k
FFs
7.34k
BRAM
0
Core clock [MHz]
~402MHz
Device Family (1)
Statix-10
Wire to Wire Round-Trip Latency (2)
134ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
4.68k
FFs
8.26k
BRAM
< 1%
Core clock [MHz]
~402MHz
25G MAC/PCS + RS-FEC
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
713ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
13.1k
FFs
14.4k
BRAM
5
Core clock [MHz]
~402MHz
Device Family (1)
Statix-10
Wire to Wire Round-Trip Latency (2)
730ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
12.5k
FFs
20.8k
BRAM
< 1%
Core clock [MHz]
~402MHz
(1) Other FPGA platforms are also supported. Performances provided for mid speed grade (-2).
(2) Latency: Transceiver + PCS + MAC (Tx + Rx)
(3) Resources utilization includes statistics counters
(2) Latency: Transceiver + PCS + MAC (Tx + Rx)
(3) Resources utilization includes statistics counters
40/100G MAC & PCS + RS-FEC
Rate [Gbps]
40G
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
315 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
Rate [Gbps]
100G (RS-FEC OFF)
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
196 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
Rate [Gbps]
100G (RS-FEC ON)
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
399 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
(1) Other FPGA platforms are also supported. Performances provided for mid speed grade (-2).
(2) Latency: Transceiver + PCS + MAC (Tx + Rx) Contact us for the performance of other product variants
(3) Resources utilization includes statistics counters
(2) Latency: Transceiver + PCS + MAC (Tx + Rx) Contact us for the performance of other product variants
(3) Resources utilization includes statistics counters
Part of a complete ultra-low latency FPGA networking stack
Orthogone’s ULL Ethernet MAC/PCS IP cores provide the foundation for deterministic FPGA networking. Combined with the ULL TCP/UDP Offload Engines and PCIe DMA controllers, they enable a complete hardware networking pipeline optimized for ultra-low latency and high-throughput data processing.
Need a fast track to develop
your FPGA-based SmartNIC solutions?
Discover our ULL FPGA Framework
Ultra-Low latency FPGA networking solutions built for performance
In latency-critical industries such as fintech, defense, telecom, HPC, and industrial IoT, network performance directly impacts competitiveness and system reliability. Ultra-low-latency FPGA IP cores provide the deterministic connectivity required to power next-generation infrastructures.
Aerospace & Defense
Industrial IoT
High-Frequency Trading
High-Performance Computing
Telecommunications
Data Centers
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Technical questions about our Ethernet IP cores
We license semiconductor IP cores and provide design services. For IP cores, we typically charge an upfront license fee which is invoiced when the product is delivered.
Yes. We have a few FPGA reference designs (Xilinx and Intel PSG) that we can provide to help you integrate the cores in your design.
Our licensing models are flexible. We offer per-project and per-site licensing options to suit your needs, your business, and your budget. Please contact us for more information.
Technical support and updates are included in the first year after delivery of the IP cores. It’s generally via email and conference calls. It is also possible to extend the support, updates and maintenance period.
