Ultra-low latency IP Cores

DESIGNED FOR ELECTRONIC/ HIGH FREQUENCY TRADING, HIGH PERFORMANCE COMPUTING (HPC), NETWORKING FUNCTIONS AND HW ACCELERATION

The industry's lowest latency network connectivity solutions

BOOST THE PERFORMANCE OF YOUR PRODUCTS

ULL Ethernet MAC/PCS

ULL TCP/IP UDP/IP Offload Engine

ULL PCle DMA Controller

Leading latency, optimized for data center

ULL Ethernet
MAC & PCS IP Cores

Solutions from 1 to 100 Gbps data rate for ultra-low latency network connectivity

High performance Ethernet MAC & PCS IP cores supporting 1G, 10G, 25G, 40/100G data rates with optional RS-FEC error correction, provide a fast and reliable solution for financial and networking applications.

They significantly reduce time-to-market and are developed using advanced design techniques, resulting in unmatched and amazing latency performance. They include a rich set of standard and advanced features that make them ideal for a wide range of applications.

Experience Unparalleled Speed and Efficiency

PRODUCT BRIEF - Ultra-Low Latency 10G MAC & PCS.

Download our product brief and unlock the power of high-speed, efficient Ethernet solutions for optimized system performance.

Download Product Brief

IP cores for FPGA developers

1G

Ultra-Low Latency
1G Ethernet MAC & PCS

10G

Ultra-Low Latency 10G Ethernet MAC & PCS

+RS-FEC

25G

25G Ethernet MAC & PCS
+ RS-FEC

+RS-FEC

40/100G

40/100G Ethernet MAC & PCS
+ RS-FEC

      ULL Ethernet MAC/PCS

  • Best in-class latency and throughput performance
  • Highly optimized implementation supporting multiple SERDES data bus width options
  • Ultra-low gate count and resources utilization
  • Excellent timing margin including a rich set of standard and advanced features
  • Based on a unified Verilog code solution that scales from 1-Gbps to 100-Gbps data rate
  • Unified Verilog source code and UVM environmentCompliant with the IEEE 802.3 High Speed Ethernet Standard
  • Compliant with the IEEE 802.3 High Speed Ethernet Standard

      Advanced features for 1-Gbps to 100-Gbps data rates

  • Frame-Check Sequence (FCS) insertion and verification at line rate
  • Full statistics on transmit and receive MAC/PCS data
  • Full wire line speed with no dropped packets for 64-byte packet length
  • Supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets
  • Ethernet MAC supports 1GbE, 10GbE, 25GbE, 40GbE and 100GbE line rate
  • Optional RS-FEC for 25- and 100-Gbps
  • Soft PCS logic interfacing to standard serial transceiver at 1.25Gbps (1G), 10.3125Gbps (10, 40G), 25.78125Gbps (25, 100G)
  • Programmable Tx and Rx path VLAN detection
  • Optional Reed Solomon FEC RS (528, 514) with FEC bypass and error correction bypass capabilities
  • Configurable statistics vector and collector on transmit and receive MAC/PCS data
     

1G MAC & PCS

Wire to Wire Round-Trip Latency (1)
136ns
Device Family (2)
UltraScale +
Rate [Gbps]
1-Gbps
Resources Utilization (3)
LUTs
2.28k
FFs
4.14k
BRAM
0
Core clock [MHz]
250
Latency Measurements
TxSoP to RxSoP
Wire to Wire Round-Trip Latency (1)
64ns
Device Family (2)
UltraScale +
Rate [Gbps]
1-Gbps
Resources Utilization (3)
LUTs
2.28k
FFs
4.14k
BRAM
0
Core clock [MHz]
250
Latency Measurements
TxSoP to RxSoF
Download 1G PDF
(1) Latency: GTY Transceiver + PCS + MAC (Tx+Rx)
(2) Other FPGA platforms supported

(3) Resources utilization includes statistics counters

10G MAC & PCS

Wire to Wire Round-Trip Latency (1)
20.2ns
Device Family
UltraScale +
Rate [Gbps]
10-Gbps
SERDES Width
16b
AXI-4 Stream Width
16b
Resources Utilization
LUTs
1.4k
FFs
1.1k
BRAM
0
Core clock [MHz]
644.531
Wire to Wire Round-Trip Latency (2)
34.1ns
Device Family
UltraScale +
Rate [Gbps]
10-Gbps
SERDES Width
16b
AXI-4 Stream Width
32b
Resources Utilization
LUTs
1.5k
FFs
1.1k
BRAM
0
Core clock [MHz]
644.531
Download 10G PDF
(1) Latency: GTY + MAC/PCS (Measured from TxSoP to RxSoF using serial loopback)
(2) Latency: GTY + MAC/PCS + CDC(Measured from TxSoP to RxSoP using serial loopback)

25G MAC/PCS

Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
114ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
4.98k
FFs
7.34k
BRAM
0
Core clock [MHz]
~402MHz
Device Family (1)
Statix-10
Wire to Wire Round-Trip Latency (2)
134ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
4.68k
FFs
8.26k
BRAM
< 1%
Core clock [MHz]
~402MHz

25G MAC/PCS + RS-FEC

Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
713ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
13.1k
FFs
14.4k
BRAM
5
Core clock [MHz]
~402MHz
Device Family (1)
Statix-10
Wire to Wire Round-Trip Latency (2)
730ns
Rate [Gbps]
25-Gbps
Resources Utilization (3)
LUTs
12.5k
FFs
20.8k
BRAM
< 1%
Core clock [MHz]
~402MHz
Download 25G MAC/PCS + RS-FEC PDF
(1) Other FPGA platforms are also supported. Performances provided for mid speed grade (-2).
(2) Latency: Transceiver + PCS + MAC (Tx + Rx)
(3) Resources utilization includes statistics counters

40/100G MAC & PCS + RS-FEC

Rate [Gbps]
40G
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
315 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
Rate [Gbps]
100G (RS-FEC OFF)
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
196 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
Rate [Gbps]
100G (RS-FEC ON)
Device Family (1)
UltraScale +
Wire to Wire Round-Trip Latency (2)
399 ns
Resources Utilization (3)
LUTs
44.2k
FFs
43.6k
BRAM
21
Core clock [MHz]
~402MHz
Download 40/100G PDF
(1) Other FPGA platforms are also supported. Performances provided for mid speed grade (-2).
(2) Latency: Transceiver + PCS + MAC (Tx + Rx) Contact us for the performance of other product variants
(3) Resources utilization includes statistics counters

Download our product brief and get additional information

1G Product Brief

10G Product Brief

25G MAC/PCS + RS-FEC

40/100G Product Brief

Request information
Contact us for a personalized evaluation

Full RTL network stacks for fast connections

ULL TCP/IP, UDP/IP
Offload Engine

The most feature-rich network protocol stacks for seamless, FPGA-enabled network connectivity

The high-performance TCP and UDP IP offload engine cores provide a fast and reliable solution for financial and networking applications. They address the data center industry's growing need for throughput and hardware acceleration and provide network protocol offload for applications such as financial data processing, reprogrammable Smart NICs, and high-performance computing.

Typical latency performances : 6.2ns Tx path (Cut-through mode, Store-and-Forward Mode (Payload ≤ 16B))

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Apply for a free 30-day
product evaluation
  • Best in-class latency and throughput performances
  • Full RTL implementation supporting layers 2, 3, 4 (ARP, IPv4, ICMP, TCP, UDP)
  • Easy to use standardize AXI-4 streaming interfaces
  • Host Processor Interface (HPI) supporting standard Linux networking stacks (non-offloaded stream)
  • Easy to integrate with Orthogone ULL Ethernet MAC/PCS solutions
  • Full interoperability testing against industry standards
  • Layer 2 through Layer 4 solution comprises:
    • ARP, IPv4, and ICMP (ping)
    • TCP and UDP
    • TCP/UDP session management
    • Configurable number of connections, up to 64 per endpoint
    • Server-side or client-side support, per connection
    • TCP congestion control via fast retransmit/recovery
    • TCP support for MSS, timestamps
    • TCP Retransmission buffer
    • Delayed Acknowledge
    • RTO computation RFC-6298
    • Checksum verification and calculation
  • Store/Forward, Cut-Through Mode
  • 32b AXI-4 @ 322MHz (MAC side)
  • On-Chip application Interface :
    • 32b AXI-4 @ 322MHz (Cut-Through Mode)
    • 128b AXI-4 @ 322MHz (Store and Forward Mode
  • Host Processor Interface (HPI) for non-offload protocols
Request information

Move data faster between FPGA-based
Smart NIC and Host CPU

ULL PCIe DMA
Controller

Offers new options for your design by supporting multiple configurations in a variety of applications

The PCIe DMA controller enables ultra-fast data transfer between FPGA logic, processors, and memory to meet the requirements of low-latency and datacenters requirements. User-friendly for software developers building low-latency network streaming applications. Easy to integrate with standard PCIe endpoint and Orthogone ULL TCP/IP, UDP/IP Offload Engine.

  • Best in-class latency and throughput performances
  • Custom multi-channel Circular Buffer DMA (CBDMA) architecture specifically designed for ULL applications
  • Easy to integrate with standard PCIe endpoint (gen. 3, gen. 4)
  • Full Kernel bypass implementation resulting in extremely low latency and jitter
  • High-quality verification based on UVM environment
  • PCIe Gen 3 (x16)
  • Ultra-fast transfer of data between FPGA logic and memory mapped user space
  • Multi-channel circular buffer architecture
  • Zero-copy circular buffers memory mapped to user space
  • Integrated with Xilinx US+ PCIe IP core
  • 250MHZ Core clock
Request information

FAQ

WE LIKE SIMPLICITY AND TRANSPARENCY

We license semiconductor IP cores and provide design services. For IP cores, we typically charge an upfront license fee which is invoiced when the product is delivered.

 
 
 
 

Yes. We have a few FPGA reference designs (Xilinx and Intel PSG) that we can provide to help you integrate the cores in your design.

 
 
 
 

Our licensing models are flexible. We offer per-project and per-site licensing options to suit your needs, your business, and your budget. Please contact us for more information.

 
 
 
 

Technical support and updates are included in the first year after delivery of the IP cores. It’s generally via email and conference calls. It is also possible to extend the support, updates and maintenance period.

 
 

Need a fast track to develop
your FPGA-based SmartNIC solutions?

Discover our ULL FPGA Framework

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Saint-Laurent, Quebec
H4S 2C9

T: 1 (514) 316-1917
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