Ultra-Low Latency PCIe Direct Memory Access IP Core for high-speed connectivity
Move data between FPGA and host memory with deterministic latency and high throughput.
In high-performance FPGA systems, moving data efficiently between the FPGA and the host CPU is critical. Software-driven transfers introduce latency, CPU overhead, and unpredictable performance under load. Modern architectures require deterministic, high-throughput PCIe data paths capable of sustaining real-time data pipelines.
When host-FPGA data transfers define system performance
Benefits
- Best in-class latency and throughput performances
- Custom multi-channel Circular Buffer DMA (CBDMA) architecture specifically designed for ULL applications
- Easy to integrate with standard PCIe endpoint (gen. 3, gen. 4)
- Full Kernel bypass implementation resulting in extremely low latency and jitter
- High-quality verification based on UVM environment
Key Features
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Flexible and Parameterizable Architecture
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Seamless FPGA and Networking Integration
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Optimized FPGA Implementation
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High-Performance DMA Architecture
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Software and Driver Ecosystem
Move data faster between FPGA-based SmartNIC and Host CPU
ULL PCIe DMA Controller
Download our product brief to unleash the potential of ultra-low latency bidirectional data transfer.
Part of an end-to-end FPGA networking architecture
Integrated with Orthogone’s Ethernet MAC/PCS and network acceleration IP cores, the DMA controller enables a complete FPGA pipeline from network ingestion to host memory transfer.
Build deterministic high-performance systems faster
The ULL FPGA Framework integrates ultra-low latency networking IP and FPGA acceleration into a ready foundation for real-time applications.
Built for the most latency-sensitive systems
Industries such as fintech, telecom, defense, and HPC require deterministic networking performance to process data at line rate. FPGA networking IP cores enable ultra-low latency data paths and predictable system behavior.
High-Performance Computing
Data Centers
High-Frequency Trading
Aerospace & Defense
Industrial IoT
Telecommunications
Developed with industry-leading technology partners
Answers to technical questions about our IP Cores
We license semiconductor IP cores and provide design services. For IP cores, we typically charge an upfront license fee which is invoiced when the product is delivered.
Yes. We have a few FPGA reference designs (Xilinx and Intel PSG) that we can provide to help you integrate the cores in your design.
Our licensing models are flexible. We offer per-project and per-site licensing options to suit your needs, your business, and your budget. Please contact us for more information.
Technical support and updates are included in the first year after delivery of the IP cores. It’s generally via email and conference calls. It is also possible to extend the support, updates and maintenance period.
