Ultra-low latency Ip cores for hardware acceleration of a trading platform
As investors have always been looking for new and innovative ways to gain an advantage over other market players, our client asked Orthogone to develop ultra-low latency, ultra-low gate count Ethernet MAC/PCS and RS-FEC IP cores to handle high-frequency transaction requests between the bank and the stock exchange, thus differentiating itself from the competition.
Orthogone used a holistic approach to develop multiple Ethernet MAC/PCS flavours to support multiple data rates and Forward Error Correction (FEC) options. A single Verilog source code platform was used to support all configurations, options, and technology process nodes. This greatly simplified test, integration and regression and preserved a uniform design for all options and configurations.
Multiple design innovations in the data processing algorithms resulted in ultra-low gate count and impressive latency performances making the cores ideal for applications where latency is critical (e.g., algorithmic trading).
The solution targets ultra-low latency execution, high transaction throughput and robustness through transmission redundancy and data compression to maximize bandwidth. Multiple deployments have been completed in different market segments and geographic locations.
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