ULL PCIe DMA Controller
Unlock High-Speed Data Transfer Between SmartNICs and Host CPU
Reduce Latency and Maximize Throughput with our ULL PCIe DMA Controller
The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe. With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.
* RTT min latency, PCIe Gen4 x 8 lanes, Xilinx/AMD x3522pv, Intel® Core™ i9-14900KS CPU @5.90GHz, Synchronous AXI-4 Interfaces (512b, 250MHz), Payload counts: 128k
An ultra-low latency data mover engineered for real-time data performance
High speed & flexibility
Obtain exceptional performance for latency-critical core applications. The ULL PCIe DMA Controller is designed using cut-through techniques to optimize latency to move data and control/status messages across the PCIe link.
Seamless FPGA Integration
In the card-to-host direction, packets are transferred through PCIe from FPGA to host buffer memory in separate memory blocks, one or many blocks depending on the packet size. In the host-to-card path, packets are transferred directly to the FPGA memory space through optimized PCIe transactions.
Kernel-Bypass Optimized for Linux Applications
Designed explicitly for Kernel-bypass Linux environments, our controller leverages a polling and ring buffer DMA architecture to support ultra-low latency needs in high-throughput systems.
High-Level Block Diagram
Experience lightning-fast, bidirectional data transfer between FPGA-based SmartNICs and Host CPU
ULL PCIe DMA Controller
635ns*
Dell/EMC PowerEdge R750
(Intel® Xeon® Gold 5315Y)
* RTT min latency, PCIe Gen4 x 8 lanes, Xilinx/AMD x3522pv, Intel(R) Xeon(R) Gold 5315Y CPU @3.20GHz, Synchronous AXI-4 Interfaces (512b, 250MHz), Payload counts: 128k
Our scalable frameworks evolve with your trading strategies, ensuring long-term performance and viability.
ULL PCIe DMA Controller
608ns*
Blackcore G3 SPR-M
(Intel® Xeon® w7-2495X)
* RTT min latency, PCIe Gen4 x 8 lanes, Xilinx/AMD x3522pv, Intel® Xeon® w7-2495X CPU @4.80GHz, Synchronous AXI-4 Interfaces (512b, 250MHz), Payload counts: 128k
ULL PCIe DMA Controller
585ns*
Blackcore ICON 3100-RL+
(Intel® Core™ i9-14900KS)
* RTT min latency, PCIe Gen4 x 8 lanes, Xilinx/AMD x3522pv, Intel® Core™ i9-14900KS CPU @5.90GHz, Synchronous AXI-4 Interfaces (512b, 250MHz), Payload counts: 128k
Move Data Faster with our Orthogone's ULL PCIe DMA Controller
Learn more about the specifications and advantages of our PCIe DMA Controller, engineered for latency-sensitive applications like high-frequency trading, networking, and HPC.
Reduce latency in host-FPGA communication with our high-performance PCIe DMA Controller
Delivering ultra-low latency, bidirectional data transfers between the host CPU and FPGA over a high-speed PCIe interface. User-friendly for software developers building low-latency network streaming applications. Easy to integrate with standard PCIe endpoint and Orthogone ULL TCP/IP, UDP/IP Offload Engine. Our PCIe DMA Controller supports both Intel and AMD processors.
General Features
Scalability
Highly parametrizable IP Core (Number of channels, Number of queues per channel, Memory size of each queue, Interfaces AXI-4 Stream bus width and synchronous or asynchronous to PCIe clock)
Easy to use
Linux kernel module provided with standard delivery packages (rpm, deb), driver created to automatically detect PCIe card for early evaluation solution, library API easily handles buffer creation, transmission and reception
Implementation
Highly efficient FPGA implementation with low resources utilization, and high timing margin on -2 and -3 Xilinx/AMD UltraScale+ FPGA
Integration
Fully integrated with AMD/Xilinx PCIe Endpoint (up to Gen 4 x8), and easy integration with Orthogone TCP/IP and UDP/IP network stacks
Data Mover Tailored for High-Performance Core Applications
Designed primarily for high-frequency trading (HFT), our PCIe Direct Memeory Access (DMA) Controller also delivers ultra-low latency bidirectional data transfer for cutting-edge applications demanding the highest level of performance.
Electronic
Trading Systems
Applications
Security
Storage
Acceleration
Networking Infrastructure
High-Performance Computing (HPC)
Our ecosystem of technological partners
Here are the answers to some frequently asked questions:
We would be happy to develop FPGA solutions that combine our IP cores with modules specifically designed for your applications. This allows us to be very competitive since we have a detailed knowledge of all our IP cores as well as many blocks readily available to develop your solutions. Depending on your requirements, it is also possible for us to provide you with a complete design package allowing you to take ownership of the developed solution. We can also provide technical support and maintenance to give you peace of mind if you want us to make changes or add new features as your product evolves.
Ultra-low gate count & resources and ultra-low latency performances are the key differentiators. Our products also have excellent timing margin and a rich set of standard and advanced features. They are based on a unified architecture where all rates and options are supported using a unique Verilog source code and UVM environment.
All our IP cores are extensively verified in simulations using a Universal Verification Environment (UVM) methodology with a full suite of tests that ensures interoperability with the IEEE 802.3 standard. The products are also ported on FPGA platforms to test performances and verify interoperability with standard network testing appliance equipment.
