SoC FPGA application design challenges, risks, and solutions

When you’re ready to start designing a new high-performance product you may be considering using an integrated solution such as Xilinx Zynq MPSoC or Intel SoC FPGAs. It’s important to consider the challenges and technical risks that come with these solutions. In this article, we’ll discuss how to overcome challenges and minimize risks for projects using high-end versions of SoC FPGA application design.

Topics:

What are SoC FPGAs?

4 challenges engineers face when designing SoC FPGA applications 

Mitigating risk when designing SoC FPGA solutions

What are SoC FPGAs?

We’ll use the Xilinx Zynq UltraScale+ MPSoC family as an example to explain what FPGA SoCs are. In a single device, these products integrate an FPGA programmable fabric with a processing system (PS) that includes a 64-bit quad-core or dual-core Arm® Cortex™-A53 and a dual-core Arm Cortex-R5.  Also included in high-end versions are an ARM Mali™-400MP Graphics Processor, H.265/264 Video Codec Unit, multiport external memory interfaces and a rich set of peripheral connectivity interfaces.

Learn more about Using FPGAs for Demanding Applications.

Designing applications that take advantage of the features and flexibility provided by SoC FPGAs requires an understanding of their complexity and the challenges that must be considered in early planning stages.

4 challenges engineers face when designing SoC FPGA applications

SoC FPGA manufacturers generally provide reference solutions, complete and accurate documentation and offer technical support; however, the devil is in the details. 

Below are 4 challenges that engineers should be prepared for when designing SoC FPGA solutions, and how to mitigate technical risks.

1. Power Management

Often overlooked, power management is probably one of the most critical parts of the design that requires special attention to ensure a reliable and robust design in production.  

Technical risk: SoC FPGA solutions commonly need more than 12 power rails, each having requirements such as load steps, slew rate, voltage limit, noise, sequencing, etc. And, different power architecture options allow for trade-offs between performance and flexibility.  

Risk mitigation: To maximize your chances of success, you must take time to design and validate power management and rely on power solutions that have been previously qualified.  If you need to accelerate your development schedule, you can partner with designers who have extensive expertise and have already worked with SoC FPGA application design with power management solutions. 

2. Moving Data Between the FPGA Fabric and the System Processors

SoC FPGAs contain multiple interconnect interfaces with configurable data bus sizes, dedicated interfaces to some peripherals, address translation, traffic QoS, etc.  

Technical risk: Moving data between the FPGA fabric, the host processor memory, and the various peripherals of each system is complicated.  Interconnect interfaces must be configured properly to work under all system conditions and configurations.   

Risk mitigation: If the product you want to design needs to move a lot of data between different interfaces quickly, it is critical that you have a well-thought-out, solid approach.  You could end up with serious performance limitations if you rush or lack expertise.  Consider reaching out to multi-disciplinary experts who have faced similar challenges and are able to confidently recommend end-to-end solutions.

3. Operating Systems (OS) for Safety Critical Applications

Industries, where functional safety is paramount frequently, require the use of RTOS (e.g. QNX, Nucleus) and development tools specifically designed for safety-critical applications. Industrial, aerospace, medical, and automotive industries will often have this requirement.  

Technical risk: To deploy a solution quickly, designers may try to take advantage of a reference framework based on Linux Operating System (OS). It’s possible to deploy a different OS on different cores to take advantage of the benefits of each of them.  An example of such an application would be to use three cores to run an RTOS responsible for all safety-critical software aspects while a fourth core could be running Linux to provide networking services such as WiFi or TCP/IP stacks to communicate with the outside world.

To design safety-critical applications, it is essential to properly architect the different software components since several resources can be shared between the different cores.

Risk mitigation:   In-depth knowledge of the different SoC FPGA application design resources (memory, interrupt controller, peripherals, FPGA fabric) as well as the functionalities and configurations of each OS is needed to design these solutions.

4. Signal Integrity

SoC FPGAs have several high-speed interfaces to move large amounts of data quickly, from SERDES links running at more than 25Gbps to DDR-4 memory interfaces, operating at 2666MT/s. 

Technical risk: If you do not take enough time to ensure the signal integrity of your PCBs, you may waste a lot of time troubleshooting afterwards.

Risk mitigation: Analyze signal integrity using simulation tools capable of accurately modeling PCBs, electronic packages, and interconnects.  Ensure that your design has enough margin over process, voltage and temperature variations.

Mitigating risks when designing SoC FPGA solutions

Mitigating risks requires a top-notch multi-disciplinary R&D team.

• Is power properly managed for reliable production? 
• Will your solution quickly transfer data between interfaces without latency or throughput issues?
• Are the different software components of a safety-critical application properly architected?  
• Can you properly analyze signal integrity? 

Before starting an SoC FPGA project, ensure that your team has the expertise and confidence to overcome these challenges and more.  

For help with certain aspects of your SoC FPGA project or to learn more about these types of solutions, contact us to maximize your potential with our cutting-edge FPGA design services.