Performance, determinism, low jitter and reliability have long been critical requirements in FinTech applications. The FPGA technology behind Orthogone Technologies’ Ultra-Low-Latency (ULL) FPGA IP Portfolio was originally developed for these demanding environments and has been deployed in production, supported and refined over several years.
Today, Orthogone is extending access to this proven technology to engineering teams across a broader range of industries, with early adopters already using the IP cores beyond FinTech, including in aerospace and defense, as well as quantum computing applications.
FPGA networking and data movement in one integrated portfolio
The ULL FPGA IP Portfolio brings together production-grade networking and data-movement IP cores for AMD UltraScale+™ and Versal™ adaptive platforms.
The portfolio combines Ethernet MAC/PCS with optional Reed-Solomon FEC, hardware TCP/IP and UDP/IP offload engines, and a PCIe® Circular-Buffer DMA controller within a single integrated development kit.
Together, these capabilities enable engineering teams to add deterministic, sub-microsecond-class networking and high-throughput packet processing to their designs without developing protocol logic from scratch.
Offloading network processing to the FPGA
The TCP/IP and UDP/IP Offload Engines move Layer 2 through Layer 4 processing into FPGA logic, delivering full throughput with best-in-class latency performance.
By moving network processing to the FPGA, the portfolio reduces the packet-processing workload on the host CPU and frees compute resources for other application tasks.
The Ethernet MAC/PCS cores provide standards-compliant IEEE 802.3 Ethernet at 1G, 10G, 25G, 40G and 100G line rates, with optional RS-FEC at 25G and 100G.
For data movement between the FPGA and host, the PCIe® Circular-Buffer DMA controller provides bidirectional transfers over PCIe Gen3/Gen4. Additional features and data rates for the networking cores are also available through a custom technical-commercial engagement with Orthogone’s engineering team.
Bringing FinTech-proven FPGA technology to more industries
While the technology behind the portfolio originated in FinTech, its capabilities are now available to engineering teams working across a broader range of demanding applications.
The portfolio addresses data center and high-performance computing, aerospace and defense, industrial and robotics, medical devices, communications, test and measurement, quantum computing and other compute-intensive applications where throughput, latency, jitter and FPGA resource efficiency all matter at once.
A complete development kit
The portfolio is delivered as an integrated kit that includes:
- Encrypted RTL source
- Reference designs for AMD Alveo™ boards
- End-to-end simulation testbenches
- A complete Linux driver stack
- Product documentation
Project, site, corporate, annualized and card-based licensing options are available.
This portfolio brings together IP originally built for some of the most latency-sensitive systems we work on. It has been deployed in production and supported for several years. It provides teams in other industries with a proven, integrated kit they can build on without starting from scratch.
Alexandre Raymond
CTO of Orthogone Technologies
The Ultra-Low-Latency FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+™ and Versal™ adaptive platforms.
Interested in learning more about Orthogone’s Ultra-Low-Latency FPGA IP Portfolio? Contact our team.
For more information about the announcement, read the full press release on Newswire.
